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Single Chip 10BASE-FL Transceiver Technical Data
HFBR-4663
General Description
The HFBR-4663 Single Chip 10BASE-FL Transceiver is a highly integrated circuit for IEEE 802.3 10Base-FL transceivers. This product, when used with HP's fiber-optic transmitters and receivers (HFBR-14X4 and HFBR-2416), ensures compliance to the 10Base-FL Standard with a minimum number of external components and board space. The HFBR-4663 offers a standard IEEE 802.3 AU interface that allows it to be directly connected to industry standard manchester encoder/decoder chips or an AUI connector. The fiber-optic LED driver offers a current drive output that directly drives the HFBR-14X4 transmitter. The data quantizer section of the HFBR4663 is directly compatible with the output of the HFBR-24X6 fiber-optic receiver and is capable of accepting input signals as low as 2 mVp-p with a 55 dB dynamic range.
The transmitter automatically inserts 1 MHz signal during idle time and removes this signal on reception. Low light is continuously monitored for both activity as well as power level. Five LED status indicators monitor error conditions as well as transmissions, receptions, and collisions.
Features
* Single Chip Solution for 10BASE-FL Internal or External Medium Attachment Units (MAUs) * Specifically Designed for Use with HFBR-14X4 and HFBR24X6 Fiber-optic Transmitters and Receivers * Incorporates an AU Interface * Highly Stable Data Quantizer with 55 dB Input Dynamic Range * Input Sensitivity as Low as 2 mVP-P
* Current Driven Fiber Optic LED Driver for Accurate Launch Power * Single +5 Volt Supply * No Crystal or Clock Required * Five Network Status LED Outputs * Available in 28 Pin PCC Package * Semi-Standard Option Available
CAUTION: The small junction sizes inherent to the design of this component increase the component's susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
5965-8597E (5/97)
77
Block Diagram
VCCTx (+5 V)
SQEN/JABD
+5 V RTSET
GND
AVCC
Tx+ Tx-
AUI RECEIVER
FIBER OPTIC LED DRIVER
TxOUT XMT
Tx SQUELCH
1 MHz IDLE SIGNAL
RCV JABBER LED DRIVERS CLSN JAB LMON
SQE
BIAS
COL+ COL-
AUI DRIVER
10 MHz GATED OSCILLATOR
RECEIVE SQUELCH
AMP Tx Rx+ RxAUI DRIVER LOOPBACK MUX Rx CMP
VIN+ VIN-
VDC VREF LINK DETECT VREF VTHADJ
RRSET GND VCC (+5 V) +5 V LBDIS AGND CTIMER
78
Pin Connection
28 - PIN PCC Q - 28
CTIMER CLSN AVCC COL+ COLVIN+ JAB
4 SQEN/JABD Rx+ RxLBDIS VCC Tx+ Tx5 6 7 8 9 10 11 12
RTSET
3
2
1
28
27
26 25 24 23 22 21 20 19 18
TxOUT
VINAGND VTHADJ VREF VDC GND GND
13
RRSET
14
LMON
15
XMT
16
RCV
17
VCCTx
TOP VIEW
Pin Description
Pin 1 2 3 4 5 Name CLSN COL+ COLCTIMER SQEN/JABD Function Indicates that a collision is taking place. Active low LED driver, open collector. Event is extended with internal timer for visibility. Gated 10 MHz oscillation used to indicate a collision, SQE test, or jabber. Balanced differential line driver outputs that meet AUI specifications. A capacitor from this pin to VCC determines the Link Monitor response time. SQE Test Enable, jabber Disable. When tied low, SQE test is disabled, when tied high SQE test is enabled. When tied to 2.0 V both SQE test and jabber are disabled. Manchester encoded receive data output to the local device. Balanced differential line driver outputs that meet AUI specifications. Loopback Disable. When this pin is tied to VCC, the AUI transmit pair data is not looped back to the AUI receive pair, and collision is disabled. When this pin is tied to GND (normal operation) or left floating, the AUI transmit pair data is looped back to the AUI receiver pair, except during collision. +5 V power input. Balanced differential line receiver inputs that meet AUI specifications. These inputs may be transformer or capacitively coupled. The Tx input pins are internally DC biased for AC coupling. Sets the current driven output of the transmitter. A 1% 61.9 k resistor tied from this pin to VCC sets the biasing currents for internal nodes. Link Monitor "Low Light" LED status output. This pin is pulled low when the voltage on the VIN+, VIN- inputs exceed the minimum threshold set by the VTHADJ pin, and there are transitions on VIN+, VIN- indicating an idle signal or active data. If either the voltage on the VIN+, VIN- inputs fall below the minimum threshold or transitions cease on VIN+, VIN-, LMON will go high. Active low LED driver, open collector. 79
6 7 8
Rx+ RxLBDIS
9 10 11 12 13 14
VCC Tx+ TxRTSET RRSET LMON
Pin Description (cont.)
Pin 15 16 Name XMT RCV Function Indicates that transmission is taking place. Active low LED driver, open collector. Event is extended with internal timer for visibility. Indicates that the transceiver is receiving a frame from the optical input. Active low LED driver, open collector. Event is extended with internal timer for visibility. +5 V supply for fiber optic LED driver. Fiber optic LED driver output. Ground Reference. Ground Reference. An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to VREF. A 2.5 V reference with respect to GND. This input pin sets the link monitor threshold. Analog Filtered Ground. This input pin should be capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately 1.3 k.) This input pin should be capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately 1.3 k.) Analog Filtered +5 V. Jabber network status LED. When in the jabber state, this pin will be low and the transmitter will be disabled. In the jabber "OK" state this pin will be high. Active low LED, open collector.
17 18 19 20 21
VCCTx TxOUT GND GND VDC
22 23 24 25 26 27 28
VREF VTHADJ AGND VINVIN+ AVCC JAB
Absolute Maximum Ratings[1]
Parameter Storage Temperature Operating Temperature Lead Soldering Cycle Temperature Lead Soldering Cycle Time Power Supply Voltage Range Input Voltage Range Input Current Output Current Symbol TS TA Min. -65 0 Max. +150 70 260 10 6.0 6.0 6.0 60 70 Units C C C sec V V V mA mA
VCC Digital Inputs (SQEN, LBDIS) Tx+, Tx-, VIN+, VINRRSET, RTSET, JAB, CLSN, XMT, RCV, LMON TxOUT
-0.3 -0.3 -0.3
80
Operating Conditions
Parameter Supply Voltage (VCC) LED on Current RRSET RTSET Min. 4.75 Typ. 5.0 10 61.9 k 1% 140 1% Max. 5.25 Units V mA
Electrical Characteristics
Unless otherwise specified, TA = 0C to 70C, VCC = VCCTx = 5 V 5% [2,3] Parameter Power Supply Current ICC: While Transmitting LED Drivers: VCC Transmit Peak Output Current[6] Transmit Squelch Voltage Level (Tx+, Tx-) Differential Output Voltage (Rx , COL ) Common Mode Output Voltage (Rx , COL ) Differential Output Voltage Imbalance (Rx , COL ) SQE/JABD SQE Test Disable Both Disabled Both Enabled Disabled Enabled 1.5 VCC - 0.5 VCC - 0.1 1 3.5 1.65 2.35 2.45 100 2 0.5 VDC = VREF (DC loop active) 50 MHz BW VIN+, VINVTHADJ = VREF[7] 0.8 -200 5 3 25 1.3 10 6 20 2.0 +200 7 1600 2.7 2.55 5 Condition VCC = 5 V, RTSET = 140 [4] IOL = 10 mA[5] RTSET = 140 47 -300 550 4.0 40 0.3 VCC - 2 52 -250 Min. Typ. Max. 220 0.8 57 -200 1200 Units mA V mA mV mV V mV V V V V V V V V mA V/V mVP-P V mV V k A mVP-P % 81
LBDIS Threshold Common Mode Voltage (Tx+, Tx-) Common Mode Voltage (VIN+, VIN-) Reference Voltage VREF Output Source Current Amplifier Gain Input Signal Range External Voltage at VTHADJ to Set VTH Input Offset Input Referred Noise Input Resistance Input Bias Current of VTHADJ Input Threshold Voltage Hysteresis
AC Electrical Characteristics
Symbol Transmit tTXNPW tTXFPW tTXLP tTXODY tTXIDF tTXDC tTXSDY tTXJ Receive tRXSFT tRXODY tRXFX tRXSDY tRXJ tAR tAF Collision tCPSQE tSQEXR tCLF tCLPDC tSQEDY tSQETD tJAD tJRT tJSQE tLED tLLPH tLLCL Collision Present to SQE Assert Time for SQE to Deactivate After Collision Collision Frequency Collision Pulse Duty Cycle SQE Test Delay (Tx Inactive to SQE) SQE Test Duration Jabber Activation Delay Jabber Reset Unjab Time Delay from Outputs Disabled to Collision Oscillator On RCV, CLSN, XMT On Time Low Light Present to LMON High Low Light Present to LMON Low 8 3 250 0 0 8.5 40 0.6 0.5 20 250 1.0 70 450 100 16 5 32 10 750 50 350 700 11.5 60 1.6 1.5 150 750 ns ns MHz % s s ms ms ns ms s ms Receive Squelch Frequency Threshold Receive Turn-On Delay Last Bit Received to Slow Decay Output Receive Steady State Propagation Delay Receive Jitter Differential Output Rise Time 20% to 80% (Rx , COL ) Differential Output Fall Time 20% to 80% (Rx , COL ) 4 4 230 300 15 50 1.5 2.51 4.5 270 MHz ns ns ns ns ns ns Transmit Turn-On Pulse Width Transmit Turn-Off Pulse Width from Data to Idle Transmit Loopback Start-up Delay Transmit Turn-On Delay Transmit Idle Frequency Transmit Idle Duty Cycle Transmit Steady State Propagation delay Transmit Jitter into 31 Load 0.85 45 15 400 20 2100 500 100 1.25 55 50 1.5 ns ns ns ns MHz % ns ns Parameter Min. Typ. Max. Units
Jabber and LED Timing
Notes: 1. Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground. 2. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 3. Low Duty Cycle pulse testing is performed at TA. 4. This does not include the current from the AUI pull-down resistors, or LED status otuputs. 5. LED drivers can sink up to 20 mA, but VOL will be higher. 6. Does not include pre-bias current for fiber optic LED which would typically be 3 mA. 7. Threshold for switching from Link Fail ot Link Pass (Low Light).
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VCC C11 0.1 R15 1.5 K D2 HLMP-1790 1 C11 MUST BE PHYSICALLY CLOSE TO U3 1 1 R14 1K 8 U3 1 14 2 6 7 3 HFBR-14X4 5 4 C5 0.1 C4 0.047 18 17 8 4 21 26 25 22 R12 0 C3 0.01 +VRF -VRF R13 00 R1 10 C1 0.1 U1 5 HFBR-24X6 C2 0.01 2 R8 100 1% 23
MON
R16 1.5 K D3 HLMP-1790
R17 1.5 K D4 HLMP-1700
R18 1.5 K D5 HLMP-1719
R19 1.5 K D6 HLMP-1790
R20 1.5 K D7 HLMP-1700
U12 1 9 2 10 3 11 4
C12 0.1
28
JAB
1
CLSN
16
RCV
15
XMT
TXOUT TXVCC LBDIS C TIMER VDC VIN+ VIN- VREF
COL-
3 R3 360
R2 360 1 2 R4 39 C13 0.1 4 5
U4 16 PE65728 15
12 5 13 6 14 7 15 8 DB 15 R11 5K (+12 VOLTS FROM AUI CONNECTOR)
COL+ TX-
2 11
U5 HFBR-4663
TX+ RX-
R5 10 39 7 R6 360 R7 360 1 C10 0.1
13 12
7 8 1 1 1 R10 3K
10 9
RX+ VTHADJ SQE
6 5
RRSET
RTSET
+VRF
-VRF
GND
GND
VCC
12
VGND
SGND
8
6
ON
1
3
7
4 -VRF
Figure 1. HFBR-4663 Schematic Diagram.
VCC
13 R9 61.9 K 1%
27
24 20
19
9
-VRF +VRF
+
10
VIN
U2 LM2574
FB OUT
3 12 L1 470 H
+
C6 22
L2 4.7 H
+
+VRF C9 0.1
6
5
4
D1 1N5817
C7 470 20%
C8 10 20% -VRF
L3 NOTES: 4.7 H 1. ALL RESISTORS 5% UNLESS OTHERWISE SHOWN. 2. ALL CAPACITORS 10% UNLESS OTHERWISE SHOWN. 3. THE HFBR-4663 DATA SHEET (PUBLICATION #5091-7391E 4/93) CONTAINS ERRORS THAT HAVE SUBSEQUENTLY BEEN CORRECTED IN THIS SCHEMATIC. 4. ALL CAPACITORS ARE IN F.
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System Description
Figure 1 shows a schematic diagram of the HFBR-4663 in an internal or external 10BASE-FL MAU. On one side of the transceiver is the AU interface and the other is the fiber optic interface. The AU interface is AC coupled when used in an external transceiver or an internal transceiver. The AU interface for an external transceiver includes isolation transformers, some biasing resistors, and a voltage regulator for power. The fiber optic side of the transceiver requires an external fiber optic transmitter and fiber optic receiver. The transmitter uses a current driven output that directly drives the fiber optic transmitter. The receive side of the transceiver accepts the data after passing through a fiber optic receiver, which consists of a module containing a pin diode and a transimpedance amplifier.
When the transceiver is external, these three pairs are AC coupled through isolation transformers, while an internal transceiver may be capacitively coupled. Tx+, Txis internally DC biased (shifted up in voltage) for the proper common mode input voltage. The two 39 1% resistors (or one 78 1% resistor) tied to he Tx+ and Tx- pins will provide the proper termination. The CI and DI pair, which are output from the transceiver to the AUI cable, require 360 pull down resistors when terminated with a 78 load. However on a DTE card, CI and DI do not need 78 terminating resistors. This also means that the pull down resistors on CI and DI can be 1 k or greater depending upon the particular Manchester encoder/ decoder chip used. Using higher value pull down resistors as in a DTE card will save power. The AUI drivers are capable of driving the full 50 meters of cable length and have a rise and fall time of typically 4 ns. In the idle state, the outputs go to the same voltage to prevent DC standing current in the isolation transformers.
low light condition. When Tx+ is more negative than Tx-, the HFBR-4663 will sink current into the chip and the fiber optic LED will emit light. Before data will be transmitted onto the fiber optic cable from the AU interface, it must exceed the squelch requirements for the DO pair. The Tx squelch circuit serves the function of preventing any noise from being transmitted onto the fiber. This circuit rejects signals with pulse widths less than typically 20 ns (negative going), or with levels less than -250 mV. Once Tx squelch circuit has unsquelched, it looks for the start of idle signal to turn on the squelch circuit again. The transmitter turns on the squelch again when it receives an input signal at Tx+, Tx- that is more positive than -250 mV for more than approximately 180 ns. At the start of a packet transmission, no more than 2 bits are received from the DO circuit and not transmitted onto the fiber optic cable. The difference between start-up delays (bit loss plus steady-state propagation delay) for any two packets that are separated by 9.6 s or less will not exceed 200 ns.
AU Interface
The AU interface consists of 3 pairs of signals, DO, CI and DI as shown in Figure 1. The DO pair contains transmit data from the DTE which is received by the transceiver and sent out onto the fiber optic cable. The DI pair contains valid data that has been either received from the fiber optic cable or looped back from the DO and output through the DI pair to the DTE. The CI pair indicates whether a collision has occurred. It is an output that oscillates at 10 MHz if a collision, jabber or SQE Test has taken place, otherwise it remains idle.
Transmission
The transmit function consists of detecting the presence of data from the AUI DO input (Tx+, Tx-) and driving that data onto the fiber optic LED transmitter. A positive signal on the Tx+ lead relative to the Tx- lead of the DO circuit will result in no current, hence the fiber optic LED is in a
Fiber Optic LED Driver
The output stage of the transmitter is a current mode switch which controls the output light by sinking current through the LED into the TxOUT pin. Once the current requirement for the LED is determined, the RTSET resistor is selected. The following equation is used to select the
84
correct RTSET resistor: RTSET=
VCC
(
52 mA ------ IOUT
)
l62
51
51 51
RTSET = 560 IOUT = 15.9 mA
The transmitter enters the idle state when it detects start of idle on Tx+ and Tx- input pins. After detecting the start of idle, the transmitter switches to a 1 MHz output idle signal. The output current is switched through the TxOUT pin during the on cycle and the VCCTx pin during the off cycle as shown in figure 2. Since the sum of the current in these two pins is constant, VCCTx should be connected as close as possible to the VCC connection for the LED. If not driving an optical LED directly, a differential output can be generated by tying resistors from VCCTx and TxOUT to VCC as shown in Figure 3. The minimum voltage on these two pins should not be less than VCC - 2 V.
ECL
VCCTx
TxOUT
Figure 3. Converting Optical LED Driver Output to Differential ECL.
Reception
The input to the transceiver comes from a fiber optic receiver as shown in figure 1. At the start of packet reception no more than 2.7 bits are received from the fiber cable and not transmitted onto the DI circuit. The receive squelch will reject frequencies lower than 2.51 MHz. While in the unsquelch state, the receive squelch circuit looks for the start of idle signal at the end of the packet. Start of idle occurs when the input signal remains idle for more than 160 ns. When start of idle is detected, the receive squelch circuit returns to the squelch state and the start of idle signal is output on the DI circuit (Rx+, Rx-).
Loopback
The loopback function emulates a 10BASE-T transceiver whereby the transmit data sent by the DTE is looped back over the AUI receive pair. Some LAN controllers use this loopback information to determine whether a MAU is connected by monitoring the carrier sense while transmitting. The software can use this loopback information to determine whether a MAU is connected to the DTE by checking the status of carrier sense after each packet transmission. When data is received by the chip while transmitting, a collision condition exits. This will cause the collision oscillator to turn on and the data on the DI pair will follow VIN+, VIN-. After a collision is detected, the collision oscillator will remain on until either DO or VIN+, VIN- go idle. Loopback can be disabled by strapping LBDIS to VCC. In this mode the chip operates as a full duplex transmitter and receiver, and collision detection is disabled. A loopback through the transceiver can be accomplished by tying the fiber transmitter to the receiver.
VCCTx
TxOUT
Collision
Whenever the receiver and the transmitter are active at the same time the chip will activate the collision output, except when loopback is disabled (LBDIS = Vcc). The collision output is a differential square wave matching the AUI specifications and capable of driving a 78 load. The frequency of the square wave is 10 MHz 15% with a 60/40 to 40/60 duty cycle. The collision oscillator also is activated during SQE Test and jabber.
IOUT
Figure 2. Fiber Optic LED Driver Structure.
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SQE Test Function Signal Quality Error
The SQE test function allows the DTE to determine whether the collision detect circuitry is functional. After each transmission, during the inter packet gap time, the collision oscillator will be activated for typically 1 s. The SQE test will not be activated if the chip is in the low light state, or the jabber on state. For SQE to operate, the SQEN pin must be tied to VCC. This allows the MAU to be interfaced to a DTE. The SQE test can be disabled by tying the SQEN pin to ground, for a repeater interface.
respective pins through a 500 resistor to 5 volts. The XMT, RCV and CLSN pins have pulse stretchers on them which enable the LEDs to be visible. When transmission or reception occurs, the LED XMT, RCV or CLSN status pins will activate low for several milliseconds. If another transmit, receive or collision condition occurs before the timer expires, the LED timer will reset and restart the timing. Therefore rapid events will leave the LEDs continuously on. The JAB and LMON LEDs do not have pulse stretchers on them since their conditions occur long enough for the eye to see.
bias voltage is set by an on-chip network at about 1.7 V. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with 3 dB corner frequency, fL, at 1 fL = -------- 21300C Since the amplifier has a differential input, two capacitors of equal value are required. If the signal driving the input is single ended, one of the coupling capacitors can be tied to AVCC as shown in Figure 1. The internal amplifier has a lowpass filter built-in to band limit the input signal which in turn will improve the signal noise ratio. Although the input is AC coupled, the offset voltage within the amplifier will be present at the amplifier's output. This is represented by VOS in Figure 4. In order to reduce this error a DC feedback loop is incorporated. This negative feedback loop nulls the offset voltage, forcing VOS to be zero. Although the capacitor on VDC is non-critical, the pole it creates can affect the stability of the feedback loop. To avoid stability problems, the value of this capacitor should be at least 10 times larger than the input coupling capacitors.
Jabber Function Requirements
The Jabber function prevents a babbling transmitter from bringing down the network. Within the transceiver is a Jabber timer that starts at the beginning of each transmission and resets at the end of each transmission. If the transmission lasts longer than 20 ms the jabber logic disables the transmitter, and turns on the collision signal COL+, COL-. When Tx+ and Tx- finally go idle, a second timer measures 0.5 seconds of idle time before the transmitter is enabled and collision is turned off. Even though the transmitter is disabled during jabber, the 1 MHz idle signal is still transmitted.
Low Light Condition
The LMON LED output is used to indicate a low light condition. LMON is activated low when both the receive power exceeds the Link Monitor threshold and there are transitions on VIN+, VIN- less than 3 s apart. If either one of these conditions do not exist, LMON will go high.
Input Amplifier
The VIN+, VIN- input signal is fed into a limiting amplifier with a gain of about 100 and input resistance of 1.3 k. Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling the input. When AC coupled, the input DC
LED Drivers
The HFBR-4663 has five LED drivers. The LED driver pins are active low, and the LEDs are normally off (except for LMON). The LEDs are tied to their
VOUT+ VOS VOUT-
Figure 4.
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The comparator is a high-speed differential zero crossing detector that slices and accurately digitizes the receive signal. The output of the comparator is fed in parallel into both the receive squelch circuit and the loopback MUX.
Link Detect Circuitry and Low Light
The link detect circuit monitors the input signal and determines when the input falls below a preset voltage level. When the input falls below a preset voltage, the HFBR-4663 goes into the Low Light state. In the Low Light state the transmitter is disabled, but continues sending the I MHz idle signal, the loopback is disabled, the receiver is disabled and the LMON LED pin goes to high shutting off the LMON LED. To return to the Link Pass state, the optical receiver power must be 20% higher than the shut-off state. This built-in hysteresis adds stability to the Link Monitor circuit. Once the receiver power threshold is exceeded, the HFBR4663 waits 250 ms to 750 ms, then checks to see that Tx+, Txis idle and no data is being received before re-enabling the transmitter, receiver, loopback circuit, and lighting up the LMON LED. The VTHADJ pin is used to adjust the sensitivity of the receiver. The HFBR-4663 is capable of exceeding the 10BASE-FL specifications for sensitivity. The sensitivity is dependent on the layout of the PC board. A good low noise layout will exceed the 10BASE-FL specifications, while a poor layout will fail to meet the sensitivity and BER spec.
The threshold generator shifts the reference voltage at VTHADJ through a circuit which has a temperature coefficient matching that of the limiting amplifier. The relationship between the VTHADJ and the VTH (the peak to peak input threshold) is: VTHADJ = 408 VTH (2)
state the link can be switched on if the input exceeds the set threshold for a time given by: CTIMER x 0.7 V T= ------------ 700 A
In a 10BASE-FL receiver, there must be less than 1 x 10-9 bit errors at a receive power level of 32.5 dBm average. One procedure to determine the sensitivity of a receiver is to start at the lowest optical power level and gradually increase the optical power until the BER is met. In this case the Link Detect circuit must not disable the receiver (i.e. VTHADJ should be tied to Ground). Once the sensitivity of the receiver is determined, VTHADJ can be set just above the power level that meets the BER specification. This way the receiver will shut-off before the BER is exceeded. For 10-BASE-FL, VTHADJ can be tied directly to VREF. However if greater sensitivity is required the circuit in Figure 5 can be used to adjust the VTHADJ voltage. Even if VREF is tied to VTHADJ, it is a good idea to layout a board with these two resistors available. This will allow potential future adjustments without board revisions. The response time of the Link Detect circuit is set by the CTIMER pin. Starting from the link off
VREF R1 VTHADJ R2
REF
THRESH GEN
Figure 5.
To switch the link from on to off, the above time will be doubled. A value of 0.05 F will meet the 10BASE-FL specifications.
Differences between 10BASE-FL and FOIRL
10BASE-FL is an improved version of the original FOIRL standard. The 10BASE-FL standard allows backward compatibility of a 10BASE-FL transceiver with a FOIRL transceiver. The main improvements incorporated into 10BASEFL are that it can attach to a DTE by adding the SQE test, and the distance has been increased from 1 km to 2 km. The other differences are much more subtle.
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1. SQE Test: The FOIRL standard did not include the option of attaching a fiber transceiver to a DTE. Adding the SQE test to 10BASE-FL enables a 10BASE-FL transceiver to attach to a DTE. 2. 0 to at Least 2 Km Distance: The FOIRL standard specifies a 1 km distance while 10BASE-FL specifies 2 km. The additional 1 km distance for 10BASE-FL comes from an increased flux budget for the cable of 3.5 dB. This 3.5 dB increase came from an increase of 2.5 dB sensitivity for the receiver and a 1 dB improvement for the transmitter. The following table illustrates the transmit and receive power requirements for the two standards. Note: FOIRL specifies optical power in peak and 10BASE-FL specifies it in average. Subtracting 3 dB from peak will give the average. In the table below the FOIRL specifications were converted from peak to average power. 3. MAU State Diagrams are Different: The state diagrams for 10BASE-FL are similar to 10BASE-T, while the state
diagrams for FOIRL are slightly different. The differences are in the AUI loopback, and in the link integrity function. AUI Loopback - In 10BASE-FL the DO to DI loopback is always disabled during a collision, and optical receive data is passed through to DI. For FOIRL there are some cases where loopback continues (i.e. DO looped to DI) during a collision, and others where loopback is disabled during a collision. 10BASE-FL is identical to 10BASE-T in this case. Please refer to the IEEE standards for greater detail.
Link Integrity - 10BASE-FL adds an additional state to the Link Integrity Test function that will not allow an exit from the Low Light State until both the transmitter and receiver are idle. In FOIRL, it is possible to exit from the Low Light State while still receiving data. MAU Timing Differences - The timing differences between 10BASE-FL and FOIRL relate to propagation delays, start-up delays, and collision deassert delays. The following table provides the details of these parameters.
Timing Parameter Differences ORD input to input on DI Steady State Prop Delay Start-Up Delay Output on DO to OTD_output Steady State Prop Delay Start-Up Delay Collision Deassert to SQE Deassert minimum
FOIRL (BIT Times) 0.5 3.5 0.5 3.5 4.5
10BASEFL (BIT Times) 2 5 2 5 0
Transmit/Receive Average Power FOIRL Transmitter Receiver 10BASE-FL Transmitter Receiver
OTD - Optical Transmit Data ORD - Optical Receive Data DI, DO, CI - AU Interface Signals
Min.
Max.
Conditions
-12 dBm -12 dBm
-21 dBm -30 dBm BER < 10-10
-12 dBm -12 dBm
-20 dBm -32.5 dBm BER < 10-9
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Timing Diagrams
tTXNPW TX+ TXVALID tTXODY TxOUT VALID tTXLP RX+ RXVALID DATA DATA DATA tTXSDY tTXFPW
Figure 6. Transmit and Loopback Timing.
VIN+ VINtRXODY RX+ RX-
VALID
DATA tRXSDY tAR VALID DATA tAF tRXFX
Figure 7. Receive Timing.
TxOUT VALID DATA
VIN+ VINtCPSQE
VALID
DATA
COL+ COLCS0
Rx+ Tx RxTx Rx Rx Rx
VIN+ VALID VINDATA
TxOUT tCPSQE
VALID
DATA
COL+ COLCS0
Figure 8. Collision Timing.
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VIN+ VIN-
TxOUT VALID tSQEXR COL+ CS0 COLDATA
Rx+ Rx RxRx Rx Tx Tx Tx
Figure 9. Collision Timing.
TxOUT
VIN+ VALID VINtSQEXR COL+ CS0 COLDATA
Rx+ RxIN RxRxIN RxIN RxIN RxIN
1 tCLF
Figure 10. Collision Timing.
TxOUT
VALID DATA
tSQETD tSQEDY
COL+ COLCS0
Figure 11. SQE Timing.
90
Tx+ TxVALID DATA
tJAD
tJRT
VALID DATA TxOUT tJSQE
COL+ COL-
Figure 12. Jabber Timing.
TxOUT
,, ,,,,
tLED XMT VIN+ VINRCV VIN+ VINtLLPH tLLCL
CS0
tLED
LMON
Figure 13. LED Timing.
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